The good old fashioned PIC microcontrollers are finding their way into new applica-tions like smartphones, gaming peripherals, audio devices and embedded solutions for eg innovative medical devices. Moreover, because the DRPIC166X has upward compatible architecture, it preserves investment in code development. And if it’s not enough, let’s just mention that DCD’s IP Core offers 1.3GHz virtual clock frequency and consumes just 37uW/MHz.
Bytom, 1st of December 2012. The DRPIC166X is a low-cost high performance 8-bit, fully static soft IP Core, intended to operate with fast (typically on-chip), dual ported memory. To fulfill modern electronics requirements, Polish IP Core has been designed with a special concern about lowest possible power consumption. It consumes just 37 uW/MHz in 0.18u technology. But power consumption means nothing without reasonable performance.
DRPIC166X is the pipelined Harvard RISC architecture, being 4 times faster, compared to original implementation. – PIC family is popular among many engineers due to low cost, wide availability, large user base and extensive collection of application notes – says Jacek Hanke, DCD’s CEO – that’s why we have not only reduced the power consumption, but also increased the performance, DRPIC166X offers 1.3 GHz virtual clock frequency in a 0.18u technological process (800 MHz virtual clock frequency in a 0.35u technology).
The DRPIC166X soft core is software-compatible with the industry standard PIC 16XXX microcontrollers. DCD’s IP Core implements an enhanced Harvard architecture (separate instruction and data memories) with independent address and data buses.
The same, it’s 4 times faster compared to the standard architecture. The 14 bit program memory and 8-bit dual port data memory allow instruction fetch and data operations, to occur simultaneously. The ad-vantage is that the instruction fetch and memory transfers can be overlapped, by multi stage pipeline, so that the next instruction can be fetched from program memory, while the current instruction is executed with data from the data memory – explains Hanke. Most instructions are executed within 1 system clock period, except the instructions which directly operate on PC (GOTO, CALL, RETURN) program counter. The pipeline is being cleared and subsequently refilled at additional one clock cycle.
The DRPIC166X Microcontroller fits perfectly in applications ranging from high-speed automotive and appliance motor control, to low-power, remote transmitters/receivers, pointing devices, telecom proces-sors or consumer electronics. Built-in power save mode, makes this IP core perfect for applications, where the power consumption aspect is critical.
The DRPIC166X is delivered with fully automated testbench, complete set of tests and DoCDTM on-chip hardware debugger, allowing easy package validation, at each stage of SoC design flow.
More information about DRPIC166X: http://www.dcd.pl/ipcore/82/drpic166x/
More information about PIC DoCDTM: http://www.dcd.pl/page/155/pic-docd/
Information about Digital Core Design:
Digital Core Design is a leading Intellectual Property (IP) Core provider and System-on-Chip (SoC) design house. The company was founded in 1999 and since the early beginning is considered as an expert in IP Cores architecture improvements. Thousands of customers became convinced by our unique solutions and billions of people worldwide use our technology in USB, MP3 players, mobile phones and many other.
The innovativeness of DCD's IP solutions has been confirmed by over 500 licenses sold to over 300 cus-tomers worldwide, such as: INTEL, SIEMENS, PHILIPS, TOYOTA, OSRAM, GENERAL ELECTRIC, SILICON GRAPHICS, RAFAEL, SAGEM or GOODRICH.
More information: http://dcd.pl/page/147/about/
For more information, please contact to:
Tomeq Cwienk, tel: + 48 32 282 82 66 ext.25, skype: tomasz.cwienk, mail to: tomasz.cwienk@dcd.pl
Digital Core Design, ul. Wroclawska 94, 41-902 Bytom, Poland