IME forms consortium to focus on developing new capabilities in bonding technologies to improve 3D chipsets to pave the way for higher-performance, slimmer and more cost- effective electronic devices
Singapore - A*STAR’s Institute of Microelectronics (IME) has formed a Chip-on-Wafer (CoW) Consortium to enable semiconductor firms to develop commercially-viable capabilities for making 3D chipsets.
The consortium focuses on enhancing a Chip-on-Wafer bonding technique with the use of Copper-Copper (Cu-Cu) diffusion bonding technology.
The members of the new consortium are ON Semiconductor, KLA-Tencor, Panasonic Factory Solutions Asia Pacific (Panasonic), Singapore Epson Industrial Pte Ltd (Plating Division), Tera Probe, Inc, and Tokyo Electron Ltd.
With the rising demand for smaller IC packages with increased functionalities, there is a pressing need to advance bonding technologies used in making memory stacks and other heterogeneous integrated circuit integration.
Conventional Chip-on-Wafer bonding techniques used for making 3D chipsets rely on a solder-assisted thermo-compression bonding process that takes more than 15 seconds and at a minimum of 300 degrees Celsius to complete. This method, which attaches the chip to a piece of semiconductor wafer, slows the overall production process and results in higher manufacturing costs.
There are also capability limitations in existing solder-assisted bonding technologies to support shrinking microelectronic systems. Melted solder bonding tends to spread and bridge with neighbouring solders, and this prevents the scaling down of the pitch, or distance between wirings in an integrated circuit.
The consortium is working on overcoming such challenges by using low temperature Cu-Cu diffusion bonding. This technique involves the diffusion of copper atoms to form metallic bonding and eliminates the long solder-assisted bonding process. This reduces overall manufacturing time and costs, and enables higher levels of 3D chipset integration.
IME and its partners have successfully demonstrated Chip-on-Wafer bonding with Cu-Cu diffusion bonding technology at a lower temperature of 200 degrees Celsius. This reduced the pitch from the average of 40 µm to 10 µm, and also lowered production costs. This allows chip device manufacturers to better integrate 3D chipsets such as CMOS image sensors, signal processors, logic and memory, and memory stacks. The consortium aims to reduce the pitch further to 6 µm to open up new possibilities in microelectronics.
Prof. Dim-Lee Kwong, Executive Director of IME, said, “We are excited to be taking the lead in this research collaboration with leading industry players by equipping them with a ready Chip-on-Wafer packaging technology. We will continue to work towards pushing the frontiers of 3D chip integration and drive market competitiveness in the value chain.”
“Joining A*STAR’s IME CoW Consortium presents a unique opportunity for KLA-Tencor to closely collaborate with leading-edge peers and share nearly 40 years of market leadership in semiconductor inspection and metrology,” said Ms. Lena Nicolaides, Vice President and General Manager of SWIFT Division at KLA-Tencor. “We’re proud to be a part of this group where our technology will enable higher yields and faster time-to-market capabilities that will lead to the creation of better performing 3D chipsets.”
“Panasonic looks forward to contribute to the consortium our expertise and experience in flip chip bonding technologies and sophisticated processes. By working closely with the consortium members, we desire to develop the next generation state-of-the-art microelectronics machine, to lead and keep abreast of the market technological trends”, said Mr. Hideki Baba, Managing Director of Panasonic.
“We strongly believe that CoW bonding technology with Cu-Cu bonding will be the breakthrough technology for future 3D IC integration. We also expect that CoW bonding technology will contribute to improve productivity and cost reduction, in addition to technology development. By combining this innovation with our WLP technology, we will like to pursue Chip-Size-Package solution for CMOS Image Sensor and Memory products,” said Mr. Yuichiro Watanabe, CEO of Tera Probe. Inc.
“Singapore Epson Plating Division is proud to be part of the Chip-on-Wafer Consortium. We believe this will serve as a key platform in advancing the development of the microelectronics industry as a whole and we certainly look forward to contributing our technological expertise together with the partners of the consortium,” said Dr. Fang Shunong, Senior General Manager of Singapore Epson Industrial Pte Ltd (Plating Division).
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